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[Other Embeded program] counterbcd

Description: 这是计数器的波形仿真文件属于vreilog的时序仿真-this is a verilog waveform file of a counter
Platform: | Size: 3072 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 用verilog语言编写的FIFO文件，这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令，希望能够帮助读者-With verilog language FIFO file, which is a traditional sequential execution method, first enter the command to finish and retire, followed by only the second instruction execution, hoping to help readers
Platform: | Size: 2048 | Author: huawei | Hits:

[VHDL-FPGA-Verilog] FSM

Description: 用verilog语言编写的FSM文件，有限个状态及在这些状态之间的转移和动作等行为的数学模型，在计算机领域有着广泛的应用。-Mathematical model with verilog language FSM file transfer and finite number of states and actions between these states and other behavior in the computer industry has a wide range of applications.
Platform: | Size: 1024 | Author: huawei | Hits:

[VHDL-FPGA-Verilog] tlk2711test

Description: 用verilog语言实现了tlk2711serdes芯片的高速串行功能，包含工程与仿真文件，亲测可用-Using Verilog language to achieve a high-speed serial tlk2711serdes chip function, including the project and the simulation file, pro test available
Platform: | Size: 14300160 | Author: 张晶晶 | Hits:

[Other] seg_display

Description: verilog语言编程，通过编程实现伪随机码的产生，程序简单易懂，易上手，带测试平台文件-verilog language programming, programming produced by pseudo-random code, the program easy to understand, approachable, with a test-platform file
Platform: | Size: 2048 | Author: 刘子易 | Hits:

[VHDL-FPGA-Verilog] pic10

Description: 本文件夹里面的是实现pic10 CPU的全部verilog代码以及相应的测试脚本代码，当然有一些模块是在quartus中直接编辑波形测试的，所以没有响应的测试脚本文件。 tri_state_port的测试还未完成，test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务 其中有三篇文档： PIC10_RISC_Design.pdf:原文（verilog代码基本都来自原文，对一部分进行了改进），这篇文章写得非常好 PIC10F200_单片机IP核的实现.pdf:对上面的文章结合自己的实验过程进行了翻译和改写，给大家参考 PIC10F:PIC10系列单片机的手册-This folder inside the pic10 CPU is to achieve all the verilog code and the corresponding test script code, of course, there are some modules in quartus directly edit the waveform test, so there is no response to the test script file. Tri_state_port test has not yet completed, test_pic10_status_reg.vt and test_pic10_tri_state_port2.vt are not complete test tasks There are three documents: PIC10_RISC_Design.pdf: the original (verilog code basically the original, on a part of the improvement), this article is written very well PIC10F200_ IP core of the realization of single-chip.pdf: The above article combined with their own experimental process of translation and rewriting, for your reference PIC10F: PIC10 family of microcontrollers
Platform: | Size: 3458048 | Author: Eddie | Hits:

[VHDL-FPGA-Verilog] tinycpufiles

Description: TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程，可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元，外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008)，可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is a Quartus project, and it can run well on Altera MAXII CPLD, and it is conveniently change to other FPGAs. The CPU used 200 Logical Cells, and the device (peripherals such as SPI, LCD) used 180 Logical Cells. It also included a assembler source code (by VC2008), which can compile the asm file for the CPU.
Platform: | Size: 60416 | Author: 肖海云 | Hits:
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